GDT data format is ( per entry):
   bits 0-15: low 16 bits of limit
   bits 16-39: low 24 bits of segment base
   bits 40-63: type
   bit  44:    1 = memory segment, 0 = system segment
   bits 45-46:  privilege level
   bit  47:    1 = present , 0 = absent
   bits 48-51: upper 4 bits of limit ( limit is only 20 bits)
   bit 52:     available for software use
   bit 53:     unused, must be 0
   bit 54:     segment type: 1 = 32 bit, 0 = 16 bit
   bit 55:     granularity: 1 = limit is page granular ( 4096 bytes),
				0 = limit is byte granular
   bit 56-63:  upper 8 bits of segment base

   for  memory type selectors (bit 44 = 1) type is one of:
 	0: read only
        2: read-write
        4: read-only, expand down limit
        6: read-write, expand down limit
        8: execute-only
        A: execute/read
        C: execute-only, conforming
        D: execute-read, conforming
   for  system type selectors ( bit 44 = 0) type is one of:
	2: LDT
	5: Task gate
	9: Available 386 TSS
	B: Busy 386 TSS
	C: 386 call gate
	E: 386 interrupt gate	( hardware interrupts)
	F: 386 trap gate	( software interrupts)

IDT data format is( per entry):
   bits 0-15: offset low 16 bits (eip)
   bits 16-31: 386 selector to use (CS)
   bits 32-36: Amount of data to copy between rings.  Means nothing
		for a hardware interrupt
   bits 37-39: unused, must be 0
   bits 40-43: type
   bit 44:	should be 0   to indicate a system type
   bits 45-46:  Priviledge level software interrupts are allowed at
   bit 47:     1 = present, 0 = absent.  Absent causes a trap
   bits 48-63: upper 16 bits of offset

   type is one of:
	5: task gate
	E: 386 interrupt gate (hardware interrupts)
 	F: 386 trap gate (software INT instruction)
   Trap gates don't disable interrupts, interrupt gates do.


Page table data format is ( per entry):
   bit 0 : 1 = present, 0 = absent
   bit 1 : 1= writeable, 0 = readonly
   bit 2 : 1 = user mode, 0 = can't access at priviledge level 3 (supervisor mode)
   bit 3,4: unused, should be 0
   bit 5,6: status bits, can be used by virtual memory systems
   bit 7-8: unused, should be 0
   bit 9-11: available to software
   bit 12-31: Upper 20 bits of the data location.  Data page tables
	refer to is always allocated on 4K boundaries.

Page table heirarchy is two-level.
   At the top level is the page directory.  It fits in one page.
   Each entry refers to a page table which maps up to 4MB of data.
   There are 1024 entries in the page table, this means with a two-level
   heirarchy you can map up to 4G.
   In the second-level page table, each entry maps a 4096-byte page
   There are 1024 entries, this means 1 page table = 4MB of memory.

   To perform paging, the processor takes the linear address formed by
   adding the memory location in question to the base of the segment in which 
   it is referred, then uses the upper 10 bits * 4 as an index into the
   page directory.  This entry in the page directory is used to find
   the page table which corresponds to the data, assuming the entry is
   present.  If it's absent you get a fault.  The next ten bits * 4 is
   used as an index into the page table which was found.  If this entry
   is present, the processor uses the upper 20 bits of it as a base physical
   address, then adds the lower 12 bits of the linear address to get
   the total physical address.

If you start playing with priviledge levels, just be aware that ring
transitions ( from a high priviledge level to a low one ) can cause a
stack switch to a more protected stack.  Part of the information stored
on that stack will be the SS:ESP you were at previously, so when a switch
to the outer ring is performed they can be restored.

Some 80386 exceptions save all the normal interrupt data on the stack ( including
SS:ESP if required) and additionally save an error code on the stack
which you are expected to parse.  Exception 8,10,11,12,13,14 fall in this
category.